In the formation of integrated circuits it is known that semiconductor substrates have been used to hold large numbers of individual active and/or passive semiconductor elements formed on the surface of one or more layers of semiconductor material deposited on a semiconductor substrate to form integrated circuits in which substantial uniformity of the elements occurs by reason of use of portions of the same epitaxial layer formed at the same time for all elements. Isolation between elements has been achieved by diffusion isolation with removal of portions of the semiconductor layers and back biasing junctions formed with no substrate. As larger and larger numbers of integrated circuits are spaced closer together in such constructions, heat dissipation either through the subsequently attached leads or through the semiconductor substrate severly limits permissible currents, power handling capabilities and/or spacing of the elements since the semiconductor substrate is a relatively poor conductor of heat. In structures of the prior art, such as power transistors, it has been known to form individual semiconductor elements, individually select and test such elements and individually mount such elements on heat sinks or the like by known means using techniques shown, for example, in U.S. Pat. No. 3,058,041 issued Oct. 9, 1962 to W. W. Happ and assigned to the same assignee as this invention. Such fabrication for integrated circuits either for operation of a plurality of individual elements in parallel, in series, or as elements performing different electrical functions is, however, expensive, particularly when the size of the elements is reduced to sizes having transverse dimensions below a few hundreths of a millimeter. Also, there is substantial nonuniformity of the composite product where the individual units were not all formed simulanteously.
When microminiature semiconductor elements are to be formed closely adjacent each other or a semiconductor wafer and the wafer is subsequently thinned by mechanical means, such as lapping or grinding, stresses in the wafer as its thickness approaches a few microns frequently can cause cracking along undesired regions of the wafer extending, for example, through active elements thereby ruining an entire group having many good elements when all of the elements of the group are subsequently formed into a single hybrid integrated circuit unit.